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e advance information march 1999 order number: 290646-002 n flexible smartvoltage technology ? 1.65 v C1.95 v read/program/erase ? 12 v for fast production programming n high performance ? 1.65 v?1.95 v: 90 ns max access time n optimized architecture for code plus data storage ? eight 4-kword blocks, top or bottom locations ? thirty one 32-kword blocks ? fast program suspend capability ? fast erase suspend capability n flexible block locking ? lock/unlock any block ? full protection on power-up ? wp# pin for hardware block protection ? v pp = gnd option ? v cc lockout voltage n low power consumption ? 9 ma typical read power ? 10 a typical standby power with automatic power savings feature n extended temperature operation ? ?40 c to +85 c n 128-bit protection register ? 64-bit unique device identifier ? 64-bit user programmable cells n extended cycling capability ? minimum 100,000 block erase cycles n supports flash data integrator software ? flash memory manager ? system interrupt manager ? supports parameter storage, streaming data (e.g., voice) n automated word program and block erase ? command user interface ? status register n cross-compatible command support ? intel basic command set ? common flash interface n x16 i/o ? 55-ball, 0.5mm pitch m bga* package ? 48-lead tsop package n 0.25 m etox? vi flash technology n improved 12 v production programming ? faster production programming ? no additional system logic the 0.25 m 1.8 volt advanced+ boot block, manufactured on intels latest 0.25 technology, represents a feature-rich solution for low power applications. these flash memory devices incorporate low voltage capability (1.65 v read, program and erase) with high-speed, low-power operation. flexible block locking allows any block to be independently locked or unlocked. a 128-bit protection register enhances customers' ability to develop secure systems. add to this the intel-devel oped flash data integrator (fdi) software and you have a cost-effective, flexible, monolithic code plus data storage solution. 1.8 volt advanced+ boot block products will be available in 48-lead tsop and 55-ball bga* packages. 1.8 volt advanced+ boot block flash memory 28F160C18 (x16)
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28F160C18 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 5937 denver, co 80217-9808 or call 1-800-548-4725 or visit intels website at http://www.intel.com copyright ? intel corporation 1999 cg-041493 * third-party brands and names are the property of their respective owners.
e 28F160C18 3 advance information contents page page 1. 0 introduction.............................................5 1.1 1.8 volt advanced+ boot block flash memory enhancements...............................5 1.2 product overview.........................................6 2. 0 product description .............................6 2.1 package pinouts ..........................................7 2.2 block organization.......................................9 2.2.1 parameter blocks .................................9 2.2.2 main blocks ..........................................9 3. 0 principles of operation.......................9 3.1 bus operation ..............................................9 3.1.1 read...................................................10 3.1.2 output disable....................................10 3.1.3 standby ..............................................10 3.1.4 reset..................................................10 3.1.5 write...................................................11 3.2 modes of operation....................................11 3.2.1 read array .........................................11 3.2.2 read configuration.............................12 3.2.3 read status register .........................12 3.2.3.1 clearing the status register ..........12 3.2.4 read query ........................................12 3.2.5 program mode....................................12 3.2.5.1 suspending and resuming program .......................................13 3.2.6 erase mode ........................................13 3.2.6.1 suspending and resuming erase..13 3.3 flexible block locking ...............................19 3.3.1 locking operation ..............................19 3.3.2 locked state ......................................19 3.3.3 unlocked state ...................................19 3.3.4 lock-down state ................................19 3.3.5 reading a blocks lock status ...........20 3.3.6 locking operations during erase suspend ............................................ 20 3.3.7 status register error checking.......... 20 3.4 128-bit protection register........................ 21 3.4.1 reading the protection register ........ 21 3.4.2 programming the protection register 21 3.4.3 locking the protection register ......... 22 3.5 v pp program and erase voltages.............. 22 3.5.1 improved 12 volt production programming ..................................... 22 3.5.2 v pp v pplk for complete protection 22 3.6 power consumption .................................. 23 3.6.1 active power (program/erase/read) . 23 3.6.2 automatic power savings (aps)........ 23 3.6.3 standby power .................................. 23 3.7 power-up/down operation........................ 24 3.7.1 rst# connected to system reset ... 24 3.7.2 v cc , v pp and rst# transitions ......... 24 3.8 power supply decoupling ......................... 24 4. 0 electrical specifications ................ 25 4.1 absolute maximum ratings....................... 25 4.2 operating conditions................................. 25 4.3 capacitance .............................................. 26 4.4 dc characteristics .................................... 26 4.5 ac characteristicsread operations extended temperature ............................. 30 4.6 ac characteristicswrite operations extended temperature ............................. 32 4.7 erase and program timings...................... 33 4.8 reset operations ...................................... 35 5.0 ordering information ........................ 36 6.0 additional information ..................... 37
28F160C18 e 4 advance information appendix a: wsm current/next states ..........38 appendix b: program/erase flowcharts ........40 appendix c: cfi query structure ...................46 appendix d: architecture block diagram ......48 appendix e: word-wide memory map diagram .......................................................49 appendix f: device id table ...........................51 appendix g: protection register addressing ..................................................52 revision history date of revision version description 03/01/99 -001 original version 03/23/99 -002 read access speed improved from 100 ns to 90 ns other minor changes
e 28F160C18 5 advance information 1.0 introduction this document contains the specifications for the intel ? 1.8 volt advanced+ boot block flash memory family, which is optimized for low power, portable systems. this family of pr oducts features a low v cc /v pp operating range 1.65 v C1.95 v for read, program, and erase operations. in addition this family is capable of fast programming at 12 v. throughout this document, the term 1.65 v refers to the full voltage range 1.65 vC1.95 v (except where noted otherwise) and v pp = 12 v refers to 12 v 5%. section 1 and 2 provides an overview of the flash memory family including applications, pinouts, pin descriptions and memory organization. section 3 describes the operation of these products and section 4 contains electrical specifications. finally, section 5 contains ordering information. 1.1 1.8 volt advanced+ boot block flash memory enhancements the 1.8 volt advanced+ boot block flash memory features: zero-latency, flexible block locking 128-bit protection register simple system implementation for 12 v production programming with 1.65 v in-field programming ultra-low power operation at 1.65 v minimum 100,000 block erase cycles common flash interface for software query of device specs and features table 1. 1.8 volt advanced+ boot block feature summary feature 16 mbit reference v cc operating voltage 1.65 v C 1.95 v table 10 v pp voltage provides complete write protection with optional 12 v fast programming table 10 v ccq i/o voltage 1.65 v C 1.95 v bus width 16-bit speed (ns) 90, 120 ns @ 1.65 v section 4.5 blocking (top or bottom) 8 x 4-kw parameter 16-mb: 31 x 32-kw main section 2.2 appendix e operating temperature extended: C40 c to +85 c table 10 program/erase cycling 100,000 cycles (minimum) table 10 packages 48-lead tsop 55-ball m bga* csp figures 1, 2 block locking flexible locking of any block with zero latency section 3.3 protection register 64-bit unique device number, 64-bit user programmable section 3.4
28F160C18 e 6 advance information 1.2 product overview the intel 1.8v advanced+ boot block flash memory provides secure low voltage memory solutions. a new block locking feature allows instant locking/unlocking of any block with zero-latency. a 128-bit protection register allows unique flash device identification. discrete supply pins provide ultra-low voltage read, program, and erase capability at 1.65 v while also allowing 12 v v pp for faster production programming. improved 12 v production programming, a new feature designed to reduce external logic, simplifies board designs when combining 12 v production programming with 1.65 v in-field programming. the 1.8 volt advanced+ boot block flash memory is available in a x16 package in the following density (see section 5, ordering information ). 16-mbit (16,777,216 bit) flash memories organized as either 1024 kwords of 16 bits each. eight 4-kword parameter blocks are located at either the top (denoted by -t suffix) or the bottom ( Cb suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. the remaining memory is grouped into 32-kword main blocks. all blocks can be locked or unlocked instantly to provide complete protection for code or data. (see section 3.3 for details). the command user interface (cui) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. the internal write state machine (wsm) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. the status register indicates the status of the wsm by signifying block erase or word program completion and status. program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the cui. program operations are performed in word increments. erase operations erase all locations within a block simultaneously. both program and erase operations can be suspended by the system software in order to read from any other block. in addition, data can be programmed to another block during an erase suspend. the 1.8 volt advanced+ boot block flash memory offers two low power savings features: automatic power savings (aps) and standby mode. the device automatically enters aps mode following the completion of a read cycle. st andby mode is initiated when the system deselects the device by driving ce# inactive. combined, these two power saving features significantly reduce power consumption. the device can be reset by lowering rst# to gnd. this provides cpu-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences (see section 3.7). refer to the dc characteristics section 4.4 for complete current and voltage specifications. refer to the ac characteristics sections 4.5 and 4.6, for read and write performance specifications. program and erase times and shown in section 4.7. 2.0 product description this section provides device pin descriptions and package pinouts for 1.8 volt advanced+ boot block flash memory, which is available in 48-lead tsop (figure 1) and 55-ball m bga packages (figure 2).
e 28F160C18 7 advance information 2.1 package pinouts advanced+ boot block 48-lead tsop 12 mm x 20 mm top view 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 25 26 27 28 29 30 31 32 16 15 7 14 6 13 5 12 4 a v ccq gnd dq dq dq dq dq dq dq dq dq v dq dq dq dq dq dq dq oe# gnd ce# a cc 11 3 10 2 9 1 8 0 0 we# rst# wp# v pp a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 nc nc figure 1. 48-lead tsop package x16 configurations nc nc nc a 14 a 10 dq 13 nc a 8 dq 12 dq 5 we# rst# nc dq 4 v pp wp# dq 11 dq 10 a 19 a 18 dq 9 dq 2 a 17 a 7 dq 0 dq 1 a 6 a 5 a 1 ce# a 4 a 3 a 2 a 0 dq 7 dq 6 nc v cc dq 3 nc dq 8 oe# v ssq nc a 15 v ccq a 11 a 12 a 16 dq 15 a 9 dq 14 a 13 gnd nc b a c d e 1 2 3 4 5 6 7 8 9 10 11 figure 2 . 55-ball bga* chip size package (top view, ball down)
28F160C18 e 8 advance information table 2. 1.8 volt advanced+ boot block pin descriptions symbol type name and function a 0 Ca 19 input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. 16-mbit x 16: a[0-19] dq 0 Cdq 7 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. inputs commands to the command user interface when ce# and we# are active. data is internally latched. outputs array, configuration and status register data. the data pins float to tri-state when the chip is de-selected or the outputs are disabled. dq 8 Cdq 15 input/output data inputs/outputs: inputs array data on the second ce# and we# cycle during a program command. data is internally latched. outputs array and configuration data. the data pins float to tri-state when the chip is de-selected. ce# input chip enable: activates the internal control logic, input buffers, decoders and sense amplifiers. ce# is active low. ce# high de-selects the memory device and reduces power consumption to standby levels. oe# input output enable: enables the devices outputs through the data buffers during a read operation. oe# is active low. we# input write enable: controls writes to the command register and memory array. we# is active low. addresses and data are latched on the rising edge of the second we# pulse. rst# input reset: uses two voltage levels (v il , v ih ) to control reset mode. when rst# is at logic low, the device is in reset which drives the outputs to high-z and resets the write state machine. when rst# is at logic high, the device is in standard operation . when rst# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. wp# input write protect: controls the lock-down function of the flexible locking feature when wp# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. when wp# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. after wp# goes low, any blocks previously marked lock-down revert to that state. see section 3.3 for details on block locking. v cc supply device power supply: [1.65 vC1.95 v] supplies power for device operations. v ccq input i/o power supply: supplies power for input/output buffers. [1.65 vC1.95 v] this input should be tied directly to v cc .
e 28F160C18 9 advance information table 2. 1.8 volt advanced+ boot block pin descriptions (continued) symbol type name and function v pp input/ supply program/erase power supply: [0.9 v C1.95 v or 11.4 vC12.6 v] operates as a input at logic levels to control complete device protection. supplies power for accelerated program and erase operations in 12 v 5% range. this pin cannot be left floating. lower v pp v pplk , to protect all contents against program and erase commands. set v pp = v cc for in-system read, program and erase operations . in this configuration, v pp can drop as low as 0.9 v to allow for resistor or diode drop from the system supply. note that if v pp is driven by a logic signal, v ih = 0.9 v. that is, v pp must remain above 0.9 v to perform in- system flash modifications. raise v pp to 12 v 5% for faster program and erase in a production environment. applying 12 v 5% to v pp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.4 for details on v pp voltage configurations. v ssq / gnd supply i/o ground / device ground: for all internal circuitry. all ground inputs must be connected. nc no connect: pin may be driven or left floating. 2.2 block organization the 1.8 volt advanced+ boot block is an asymmetrically-blocked architecture that enables system integration of c ode and data within a single flash device. each block can be erased independently of the others up to 100,000 times. for the address locations of each block, see the memory maps in appendix e. 2.2.1 parameter blocks the 1.8 volt advanced+ boot block flash memory architecture includes parameter blo cks to facilitate storage of frequently updated small parameters (i.e., data that would normally be stored in an eeprom). each device contains eight parameter blocks of 4-kwords. 2.2.2 main blocks after the parameter blocks, the remai nder of the array is divided into equal size 32-kword main blocks for data or c ode storage. the 16-mbit contains 31 main blocks. 3.0 principles of operation the 1.8 volt advanced+ boot block flash memory architecture utilizes a cui and automated algorithms to simplify program and erase operations. the cui allows for 100% cmos - level control inputs and fixed power supplies during erasure and programming. the internal wsm completely automates program and erase operations while the cui signals the start of an operation and the status register reports status. the cui handles the we# interface to the data and address latches, as well as system status requests during wsm operation. 3.1 bus operation the 1.8 volt advanced+ boot block flash memory devices read, program and erase in - system via the local cpu or microcontroller. all bus cycles to or from the flash memory conform to standard microcontroller bus cycles. four control pins dictate the data flow in and out of the flash component: ce#, oe#, we# and rst#. these bus operations are summarized in table 3.
28F160C18 e 10 advance information table 3. bus operations mode note rst# ce# oe# we# dq 0 C15 read (array, status, configuration, or query) 2,3 v ih v il v il v ih d out output disable 1 v ih xv ih x high z standby 1 v ih v ih x x high z reset 1,5 v il x x x high z write 4,5 v ih v il v ih v il d in notes: 1. x must be v il , v ih for control pins and addresses. 2. see dc characteristics for v pplk , v pp1 and v pp2 voltages. 3. manufacturer and device codes may also be accessed in read configuration mode (a 1 Ca 19 = 0). see table 4. 4. refer to table 5 for valid d in during a write operation. 5. to program or erase the lockable blocks, hold wp# at v ih . 3.1.1 read the flash memory has four read modes available: read array, read configuration, read status and read query. these modes are accessible independent of the v pp voltage. the appropriate read mode command must be issued to the cui to enter the corresponding mode. upon initial device power - up or after exit from reset, the device automatically defaults to read array mode. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control; when active it enables the flash memory device. oe# is the data output control and it drives the selected memory data onto the i/o bus. for all read modes, we# and rst# must be at v ih . figure 7 illustrates a read cycle. 3.1.2 output disable with oe# at a logic - high level (v ih ), the device outputs are disabled. output pins are placed in a high - impedance state. 3.1.3 standby deselecting the device by bringing ce# to a logic - high level (v ih ) places the device in standby mode, which substantially reduces device power consumption without any latency for subsequent read accesses. in standby, outputs are placed in a high-impedance state independent of oe#. if deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 reset from read mode, rst# at v il for time t plph deselects the memory, places output drivers in a high - impedance state, and turns off all internal circuits. after return from reset, a time t phqv is required until the initial read access outputs are valid. a delay (t phwl or t phel ) is required after return from reset before a write can be initiated. after this wake - up interval, normal operation is restored. the cui resets to read array mode, the status register is set to 80h, and all blo cks are locked. this case is shown in figure 9a.
e 28F160C18 11 advance information if rst# is taken low for time t plph during a program or erase operation, the operation will be aborted and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, since the data may be partially erased or written. the abort process goes through the following sequence: when rst# goes low, the device shuts down the operation in progress, a process which takes time t plrh to complete. after this time t plrh , the part will either reset to read array mode (if rst# has gone high during t plrh , figure 9b) or enter reset mode (if rst# is still logic low after t plrh , figure 9c). in both cases, after returning from an aborted operation, the relevant time t phqv or t phwl /t phel must be waited before a read or write operation is initiated, as discussed in the previous paragraph. however, in this case, these delays are referenced to the end of t plrh rather than when rst# goes high. as with any automated device, it is important to assert rst# during system reset. w hen the system comes out of reset, processor expects to read from the flash memory. automated flash memories provide status information when read during program or block erase operations. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intel? flash memories allow proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same reset# signal that resets the system cpu. 3.1.5 write a write takes place when both ce# and we# are low and oe# is high. commands are written to the command user interface (cui) using standard microprocessor write timings to control flash operations. the cui does not occupy an addressable memory location. the address and data buses are latched on the rising edge of the second we# or ce# pulse, whichever occurs first. figure 8 illustrates a program and erase operation. the available commands are shown in table 6, and appendix a provides detailed information on moving between the different modes of operation using cui commands. there are two commands that modify array data: program (40h) and erase (20h). writing either of these commands to the internal command user interface (cui) initiates a sequence of internally - timed functions that culminate in the completion of the requested task (unless that operation is aborted by either rst# being driven to v il for t plrh or an appropriate suspend command). 3.2 modes of operation the flash memory has four read modes and two write modes. the read modes are read array, read configuration, read status, and read query. the write modes are program and block erase. three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. these modes are reached using the commands summarized in tables 5 and 6. a comprehensive chart showing the state transitions is in appendix a. 3.2.1 read array when rst# transitions from v il (reset) to v ih , the device defaults to read array mode and will respond to the read control inputs (ce#, address inputs, and oe#) without any additional cui commands. when the device is in read array mode, four control signals control data output: we# must be logic high (v ih ) ce# must be logic low (v il ) oe# must be logic low (v il ) rst# must be logic high (v ih ) in addition, the address of the desired location must be applied to the address pins. if the device is not in read array mode, as would be the case after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can take place.
28F160C18 e 12 advance information 3.2.2 read configuration the read configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in table 4 retrieve the specified information. to return to read array mode, write the read array command (ffh). table 4. read configuration table item address data manufacturer code (x16) 00000 0089 device id (see appendix f) 00001 id block lock configuration (2) xx002 (1) lock block is unlocked dq 0 = 0 block is locked dq 0 = 1 block is locked-down dq 1 = 1 protection register lock (3) 80 pr-lock protection register 81 C88 pr notes: 1. xx specifies the block address of lock configuration being read. 2. see section 3.3 for valid lock status outputs. 3. see section 3.4 for protection register information. 4. other locations within the configuration address space are reserved by intel for future use. 3.2.3 read status register the status register indicates the status of device operations, and the success/failure of that operation. the read status register (70h) command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the array, issue a read array (ffh) command. the status register bits are output on dq 0 Cdq 7 . the upper byte, dq 8 Cdq 15 , outputs 00h during a read status register command. the contents of the status register are latched on the falling edge of oe# or ce#, whichever occurs last. this prevents possible bus errors which might occur if status register contents change while being read. ce# or oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, sr.7 will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the desired operation (see table 7). 3.2.3.1 clearing the status register the wsm sets status bits 1 through 7 to 1, and clears bits 2, 6 and 7 to 0, but cannot clear status bits 1 or 3 through 5 to 0. because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the use of the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in s equence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note that the read array command must be issued before data can be read from the memory array. resetting the device also clears the status register. 3.2.4 read query the read query mode outputs common flash interface (cfi) data when the device is read. this can be accessed by writing the read query command (98h). the cfi data structure contains information such as block size, density, command set and electrical specifications. once in this mode, read cycles from addresses shown in appendix c retrieve the specified information. to return to read array mode, write the read array command (ffh). 3.2.5 program mode programming is executed using a two - write sequence. the program setup command (40h) is written to the cui followed by a second write which specifies the address and data to be programmed.
e 28F160C18 13 advance information the wsm will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. programming the memory results in specific bits within an address location being changed to a 0. if the user attempts to program 1s, the memory cell contents do not change and no error occurs. the status register indicates programming status: while the program sequence executes, status bit 7 is 0. the status register can be polled by toggling either ce# or oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit sr.4 of the status register is set to indicate a program failure. if sr.3 is set then v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read array mode. 3.2.5.1 suspending and resuming program the program suspend command halts an in - progress program operation so that data can be read from other locations of memory. once the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). the device continues to output status register data after the program suspend command is written. polling status register bits sr.7 and sr.2 will determine when the program operation has been suspended (both will be set to 1). t whrh1 /t ehrh1 specify the program suspend latency. a read array command can now be written to the cui to read data from blo cks other t han that which is suspended. the only other valid commands, while program is suspended, are read status register, read configuration, read query, and program resume. after the program resume command is written to the flash memory, the wsm will continue with the programming process and status register bits sr.2 and sr.7 will automatically be cleared. the device automatically outputs status register data when read (see figure 11 in appendix b, program suspend/resume flowchart ) after the program resume command is written. v pp must remain at the same v pp level used for program while in program suspend mode. rst# must also remain at v ih . 3.2.6 erase mode to erase a block, write the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to 1. only one block can be erased at a time. the wsm will execute a sequence of internally timed events to program all bits within the block to 0, erase all bits within the block to 1, then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a 0. when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr.5 of the status register will be set to a 1, indicating an erase failure. if v pp was not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr.5 of the status register is set to indicate an erase error, and sr.3 is set to a 1 to identify that v pp supply voltage was not within acceptable limits. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 3.2.6.1 suspending and resuming erase since an erase operation requires on the order of seconds to complete, an erase suspend command is provided to allow erase - sequence interruption in order to read data from or program data to another
28F160C18 e 14 advance information block in memory. once the erase sequence is started, writing the erase suspend command to the cui suspends the erase sequence at a predetermined point in the erase algorithm. the device continues to output status register data after the erase suspend command is written. polling status register bits sr.6 and sr.7 will determine when the erase operation has been suspended (both will be set to 1). t whrh2 /t ehrh2 specify the program suspend latency. a read array/program command can now be written to the cui to read/program data from/to blocks other t han that which is suspended. this nested program command can subsequently be suspended to read yet another location. the only other valid commands while erase is suspended are read status register, read configuration, read query, program setup, program resume, erase resume, and lock setup. during erase suspend mode, the chip can be placed in a pseudo - standby mode by taking ce# to v ih . this reduces active current consumption. issuing the erase resume command continues the erase sequence (when ce# = v il ) and status register bits sr.6 and sr.7 will automatically be cleared. the device automatically outputs status register data when read (see figure 13 in appendix b, erase suspend/resume flowchart ) after the erase resume command is written. rst# must also remain at v ih . as with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
e 28F160C18 15 advance information table 5. command bus definitions first bus cycle second bus cycle command notes oper addr data oper addr data read array 4 write ba ffh read configuration 2, 4 write ia 90h read ia id read query 2, 4 write qa 98h read qa qd read status register 4 write ba 70h read ba srd clear status register 4 write ba 50h program 3,4 write wa 40h/10h write wa wd block erase/confirm 4 write ba 20h write ba d0h program/erase suspend 4 write ba b0h program/erase resume 4 write ba d0h lock block 4 write ba 60h write ba 01h unlock block 4 write ba 60h write ba d0h lock-down block 4 write ba 60h write ba 2fh protection program 4 write pa c0h write pa pd notes: 1. bus operations are defined in table 3. 2. following the read configuration or read query commands, read operations output device configuration or cfi query information, respectively. see section 3.2.2 and 3.2.4. 3. either 40h or 10h command is valid, but the intel standard is 40h. 4. when writing commands, the upper data bus [dq 8 Cdq 15 ] should be either v il or v ih , to minimize current draw. 5. first cycle command addresses should be the same as the operations target address. examples: the first-cycle address for the read device identification codes command should be the same as the identification code address (ia); the first cycle address for the program command should be the same as the word address (wa) to be programmed; the first cycle address for the erase/program suspend command should be the same as the address within the block to be suspended; etc. ia = identification code address. ba = address within the block.. pa = user programmable 4-word protection address in the device identification plane. qa = query code address. wa = word address of memory location to be written. srd = data read from the status register. wd = data to be written at location wa is latched on the rising edge of we# or ce# (whichever goes high first). id = identification code data. pd = user programmable 4-word protection data. qd = query code data.
28F160C18 e 16 advance information table 6. command codes and descriptions code device mode description ff read array places device in read array mode, such that array data will be output on the data pins. 40 program set-up this is a two - cycle command. the first cycle prepares the cui for a program operation. the second cycle latches addresses and data information and initiates the wsm to execute the program algorithm. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 3.2.5. 20 erase set-up prepares the cui for the erase confirm command. if the next command is not an erase confirm command, then the cui will (a) set both sr.4 and sr.5 of the status register to a 1, (b) place the device into the read status register mode, and (c) wait for another command. see section 3.2.6. d0 erase confirm program/erase resume unlock block if the previous command was an erase set-up command, then the cui will close the address and data latches, and begin erasing the block indicated on the address pins. during program/erase, the device will respond only to the read status register, program suspend and erase suspend commands and will output status register data when ce# or oe# is toggled. if a program or erase operation was previously suspended, this command will resume that operation. if the previous command was configuration set-up, the cui will latch the address and unlock the block indicated on the address pins. if the block had been previously set to lock-down, this operation will have no effect. (sect. 3.3) b0 program suspend erase suspend issuing this command will begin to suspend the currently executing program/erase operation. the status register will indicate when the operation has been successfully suspended by setting either the program suspend (sr.2) or erase suspend (sr.6) and the wsm status bit (sr.7) to a 1 (ready). the wsm will continue to idle in the suspend state, regardless of the state of all input control pins except rst#, which will immediately shut down the wsm and the remainder of the chip if rst# is driven to v il . see sections 3.2.5.1 and 3.2.6.1. 70 read status register this command places the device into read status register mode. reading the device will output the contents of the status register, regardless of the address presented to the device. the device automatically enters this mode after a program or erase operation has been initiated. see section 3.2.3. 50 clear status register the wsm can set the block lock status (sr.1) , v pp status (sr.3), program status (sr.4), and erase status (sr.5) bits in the status register to 1, but it cannot clear them to 0. issuing this command clears those bits to 0. 90 read configuration puts the device into the read configuration mode, so that reading the device will output the manufacturer/device codes or block lock status. section 3.2.2. 60 configuration set-up prepares the cui for changes to the device configuration, such as block locking changes. if the next command is not block unlock, block lock, or block lock- down, then the cui will set both the program and erase status register bits to indicate a command sequence error. see section 3.3.
e 28F160C18 17 advance information table 6. command codes and descriptions (continued) code device mode description 01 lock-block if the previous command was configuration set-up, the cui will latch the address and lock the block indicated on the address pins. (section 3.3) 2f lock-down if the previous command was a configuration set-up command, the cui will latch the address and lock-down the block indicated on the address pins. (section 3.3) 98 read query puts the device into the read query mode, so that reading the device will output common flash interface information. see section 3.2.4 and appendix c. c0 protection program setup this is a two-cycle command. the first cycle prepares the cui for an program operation to the protection register. the second cycle latches addresses and data information and initiates the wsm to execute the protection program algorithm to the protection register. the flash outputs status register data when ce# or oe# is toggled. a read array command is required after programming to read array data. see section 3.4. 10 alt. prog set-up operates the same as program set - up command. (see 40h/program set-up) 00 invalid/ reserved unassigned commands that should not be used. intel reserves the right to redefine these codes for future functions. note: see appendix a for mode transition information.
28F160C18 e 18 advance information table 7. status register bit definition wsms ess es ps vpps pss bls r 76543210 notes: sr.7 write state machine status 1 = ready (wsms) 0 = busy check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. sr.6 = erase - suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to 1. ess bit remains set to 1 until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erase 0 = successful block erase when this bit is set to 1, wsm has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in programming 0 = successful programming when this bit is set to 1, wsm has attempted but failed to program a word. sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok the v pp status bit does not provide continuous indication of v pp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered, and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. the v pp status bit is not guaranteed to report accurate feedback between v pplk max and v pp1 min or between v pp1 max and v pp2 min. sr.2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to 1. pss bit remains set to 1 until a program resume command is issued. sr.1 = block lock status 1 = prog/erase attempted on a locked block; operation aborted. 0 = no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr.0 = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register. note: 1. a command sequence error is indicated when sr.4, sr.5, and sr.7 are set
e 28F160C18 19 advance information 3.3 flexible block locking the intel 1.8 volt advanced+ boot block architecture offers an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. this locking scheme offers two levels of protection. the first level allows software-only control of block locking (useful for data blocks that c hange frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). the following sections will discuss the operation of the locking system. the term state [xyz] will be used to specify locking states; e.g., state [001], where x = value of wp#, y = bit dq 1 of the block lock status register, and z = bit dq 0 of the block lock status register. table 9 defines all of these possible locking states. 3.3.1 locking operation the following concisely summarizes the locking functionality. all blocks power-up locked, t hen can be unlocked or locked with the unlock and lock commands. the lock-down command lo cks a block and prevents it from being unlocked when wp# = 0. ? when wp# = 1, lock-down is overridden and commands can unlock/lock locked- down blocks. ? when wp# returns to 0, locked-down blocks return to lock-down. ? lock-down is cleared only when the device is reset or powered-down. the locking status of each block can set to locked, unlocked, and lock-down, each of which will be described in the following sections. a comprehensive state table for the locking functions is shown in table 9, and a flowchart for locking operations is shown in figure 14. 3.3.2 locked state the default status of all blocks upon power-up or reset is locked (states [001] or [101]). locked blocks are fully protected from alteration. any program or erase operations attempted on a locked block will return an error on bit sr.1 of the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. an unlocked block can be locked by writing the lock command sequence, 60h followed by 01h. 3.3.3 unlocked state unlocked blocks (states [ 000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by writing the unlock command sequence, 60h followed by d0h. 3.3.4 lock-down state blocks that are locked-down (state [ 011]) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked- down by writing the lock-down command sequence, 60h followed by 2fh. locked-down blocks revert to the locked state w hen the device is reset or powered down. the lock-down function is dependent on the wp# input pin. when wp# = 0, blo cks in lock-down [011] are protected from program, erase, and lock status changes. when wp# = 1, the lock-down function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. these blocks can t hen be relocked [111] and unlocked [110] as desired while wp# remains high. when wp# goes low, blo cks that were previously locked-down return to the lock-down state [011] regardless of any changes made while wp# was high. device reset or power- down resets all blocks, including those in lock- down, to locked state.
28F160C18 e 20 advance information 3.3.5 reading a blocks lock status the lock status of every block can be read in the configuration read mode of the device. to enter this mode, write 90h to the device. subsequent reads at block address + 00002 will output the lock status of that block. the lock status is represented by the lowest two output pins, dq 0 and dq 1 . dq 0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock-down. dq 1 indicates lock-down status and is set by the lock-down command. it cannot be cleared by software, only by device reset or power- down. table 8. block lock status item address data block lock configuration xx002 lock block is unlocked dq 0 = 0 block is locked dq 0 = 1 block is locked-down dq 1 = 1 3.3.6 locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command (b0h), then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. refer to appendix a for detailed information on which commands are valid during erase suspend. 3.3.7 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. since locking changes are performed using a two cycle comm and sequence, e.g., 60h followed by 01h to lock a block, following the configuration setup command (60h) with an invalid command will produce a lock command error (sr.4 and sr.5 will be set to 1) in the status register. if a lock command error occurs during an erase suspend, sr.4 and sr.5 will be set to 1, and will remain at 1 after the erase is resumed. when erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. a similar situation happens if an error occurs during a program operation error nested within an erase suspend.
e 28F160C18 21 advance information table 9. block locking state transitions current state erase/prog lock command input result [next state] wp# dq 1 dq 0 name allowed? lock unlock lock-down 000 unlocked yes goes to [001] no change goes to [011] 0 0 1 locked (default) no no change goes to [000] goes to [011] 0 1 1 locked-down no no change no change no change 1 0 0 unlocked yes goes to [101] no change goes to [111] 1 0 1 locked no no change goes to [100] goes to [111] 1 1 0 lock-down disabled yes goes to [111] no change goes to [111] 1 1 1 lock-down disabled no no change goes to [110] no change notes: 1. in this table, the notation [xyz] denotes the locking state of a block, where x = wp#, y = dq 1 , and z = dq 0 . the current locking state of a block is defined by the state of wp# and the two bits of the block lock status (dq 0 , dq 1 ). dq 0 indicates if a block is locked (1) or unlocked (0). dq 1 indicates if a block has been locked-down (1) or not (0). 2. at power-up or device reset, all blocks default to locked state [001] (if wp# = 0). holding wp# = 0 is the recommended default. 3. the erase/program allowed? column shows whether erase and program operations are enabled (yes) or disabled (no) in that blocks current locking state. 4. the lock command input result [next state] column shows the result of writing the three locking commands (lock, unlock, lock-down) in the current locking state. for example, goes to [001] would mean that writing the command to a block in the current locking state would change it to [001]. 3.4 128-bit protection register the advanced+ boot block architecture includes a 128-bit protection register than can be used to increase the security of a system design. for example, the number contained in the protection register can be used to mate the flash component with other system com ponents such as the cpu or asic, preventing device substitution. additional application information can be found in intel application note ap-657 designing with the advanced+ boot block flash memory architecture . the 128-bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the intel factory with a unique 64-bit number, which is unchangeable. the other segment is left blank for customer designs to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming. 3.4.1 reading the protection register the protection register is read in the configuration read mode. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in appendix g retrieve the specified information. to return to read array mode, write the read array command (ffh). 3.4.2 programming the protection register the protection register bits are programmed using the two-cycle protection program comm and. the 64-bit number is programmed 16 bits at a time. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. the allowable addresses are shown in appendix g. see figure 15 for the protection register programming flowchart .
28F160C18 e 22 advance information attempts to address protection program commands outside the defined protection register address space should not be attempted. this space is reserved for future use. attempting to program to a previously locked protection register segment will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). 3.4.3 locking the protection register the user-programmable segment of the protection register is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. this bit is set using the protection program command to program fffd to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). protection register lockout state is not reversible. 4 words factory programmed 4 words user programmed pr lock 88h 85h 84h 81h 80h 0645_05 figure 3. protection register memory map 3.5 v pp program and erase voltages intel 1.8 volt advanced+ boot block products provide in-system programming and erase in the 0.9 vC1.95 v range. for fast production programming, it also includes a low-cost, backward- compatible 12 v programming feature. 3.5.1 improved 12 volt production programming when v pp is between 0.9 v and 1.95 v, all program and erase current is drawn through the v cc pin. note that if v pp is driven by a logic signal, v ih min = 0.9 v. that is, v pp must remain above 0.9 v to perform in-system flash modifications. w hen v pp is connected to a 12 v power supply, the device draws program and erase current directly from the v pp pin. this eliminates the need for an external switching transistor to control the voltage v pp . figure 4 shows examples of how the flash power supplies can be configured for various usage models. the 12 v v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to v pp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 3.5.2 v pp v pplk for complete protection in addition to the flexible block locking, the v pp programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. when v pp is below v pplk , any program or erase operation will result in a error, prompting the corresponding status register bit (sr.3) to be set.
e 28F160C18 23 advance information v cc v pp 12 v fast programming absolute write protection with v pp v pplk system supply 12 v supply 10 k w v cc v pp system supply 12 v supply low voltage and 12 v fast programming v cc v pp system supply prot# (logic signal) v cc v pp system supply low-voltage programming low-voltage programming absolute write protection via logic signal (note 1) 0646_02 note: 1. a resistor can be used if the v cc supply can sink adequate current based on resistor value. techniques used in ap-657 designing with the advanced+ boot block flash memory architecture can be applied to determine resistor or diode specifications. figure 4. example power supply configurations 3.6 power consumption intels flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. the automatic power savings (aps) feature reduces power consumption when the device is selected but idle. if the ce# is deasserted, the flash enters its standby mode, where current consumption is even lower. the combination of these features can minimize memory power consumption, and therefore, overall system power consumption. 3.6.1 active power (program/erase/read) with ce# at a logic - low level and rst# at a logic - high level, the device is in the active mode. refer to the dc characteristic tables for i cc current values. active power is the largest contributor to overall system power consumption. minimizing the active current could have a profound effect on system power consumption, especially for battery - operated devices. 3.6.2 automatic power savings (aps) automatic power savings provides low - power operation during read mode. after data is read from the memory array and the address lines are quiescent, aps circuitry places the device in a mode where typical current is comparable to i ccs . the flash stays in this static state with outputs valid until a new location is read. 3.6.3 standby power with ce# at a logic - high level (v ih ) and device in read mode, the flash memory is in standby mode, which disables much of the devices circuitry and substantially reduces power consumption. outputs are placed in a high - impedance state independent of the status of the oe# signal. if ce# transitions to a logic - high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
28F160C18 e 24 advance information system engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. this will provide a more accurate measure of application - specific power and energy requirements. 3.7 power-up/down operation the device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, v pp or v cc , powers-up first. 3.7.1 rst# connected to system reset the use of rst# during system reset is important with automated program/erase devices since the system expects to r ead from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting rst# to the system cpu reset# si gnal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when v cc voltages are above v lko . since both we# and ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two- step command sequences. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (rst# connected to system powerg ood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.7.2 v cc , v pp and rst# transitions the cui latches commands as issued by system software and is not altered by v pp or ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after v cc transitions above v lko (lockout voltage), is read array mode. after any program or block erase operation is complete (even after v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. 3.8 power supply decoupling flash memorys power switching characteristics require careful device decoupling. system designers should consider three supply current issues: 1. standby current levels (i ccs ) 2. read current levels (i ccr ) 3. transient peaks produced by falling and rising edges of ce#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc and gnd, and between its v pp and gnd. these high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
e 28F160C18 25 advance information 4.0 electrical specifications 4.1 absolute maximum ratings extended operating temperature during read........................... C40 c to +85 c during block erase and program.......................... C40 c to +85 c temperature under bias........ C40 c to +85 c storage temperature ................. C65 c to +125 c voltage on any pin (except v cc and v pp ) with respect to gnd ............. C0.5 v to +3.0 v 1 v pp voltage (for block erase and program) with respect to gnd .......C0.5 v to +13.5 v 1,2,4 v cc and v ccq supply voltage with respect to gnd ............. C0.2 v to +3.7 v 5 output short circuit current...................... 100 ma 3 notice: this datasheet contains information on products in the sampling and initial phases of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. * warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may effect device reliability. notes: 1. minimum dc voltage is C0.5 v on input/output pins, with allowable undershoot to C2.0 v for periods < 20 ns. maximum dc voltage on input/output pins is v cc + 0.5 v, with allowable overshoot to v cc + 1.5 v for periods < 20 ns. 2. maximum dc voltage on v pp may overshoot to +14.0 v for periods < 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. v pp voltage is normally 0.9 vC1.95 v. connection to supply of 11.4 vC12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.5 for details. 5. minimum dc voltage is C0.5 v on v cc and v ccq , with allowable undershoot to C2.0 v for periods < 20 ns. maximum dc voltage on v cc and v ccq pins is v cc + 0.5 v, with allowable overshoot to v cc + 1.5 v for periods < 20 ns. 4.2 operating conditions table 10. temperature and voltage operating conditions symbol parameter notes min max units t a operating temperature C40 +85 c v cc1 v cc supply voltage 1 1.65 1.95 volts v ccq1 i/o supply voltage 1 1.65 1.95 volts v pp1 supply voltage, when used as logic control 1 0.9 1.95 volts v pp2 1, 2 11.4 12.6 volts cycling block erase cycling 2 100,000 cycles notes: 1. v cc and v ccq must share the same supply. 2. applying v pp = 11.4 v C12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.5 for details .
28F160C18 e 26 advance information 4.3 capacitance t a = 25 c, f = 1 mhz sym parameter notes typ max units conditions c in input capacitance 1 6 8 pf v in = 0 v c out output capacitance 1 10 12 pf v out = 0 v note: 1. sampled, not 100% tested. 4.4 dc characteristics v cc 1.65 v C1.95 v v ccq 1.65 vC1.95 v sym parameter note typ max unit test conditions i li input load current 1,7 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1,7 0.2 1a v cc = v cc max v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current 1 10 15 a v cc = v cc max ce# = rst# = v ccq rst# = wp# = v ccq or gnd v in = v ccq or gnd i ccr v cc read current 1,5,7 9 15 ma v cc = v cc max v ccq = v ccq max oe# = v ih , ce# = v il f = 5 mhz, i out = 0 ma inputs = v il or v ih i ccw + i ppw program current 1,4 30 55 ma v pp = v pp1 program in progress 18 35 ma v pp = v pp2 (12 v) program in progress i cce + i ppe erase current 1,4 30 45 ma v pp = v pp1 erase in progress 16 35 ma v pp = v pp2 (12 v) erase in progress
e 28F160C18 27 advance information 4.4 dc characteristics, continued v cc 1.65 v C1.95 v v ccq 1.65 vC1.95 v sym parameter note typ max unit test conditions i cces v cc erase suspend current 1,2,4 5 15 a ce# = v ih , erase suspend in progress i ccws v cc program suspend current 1,2,4 5 15 a ce# = v ih , program suspend in progress i pps v pp standby current 1 0.5 1 a v pp v cc i ppr v pp read current 1 0.5 1 a v pp v cc 1,4 50 200 a v pp 3 v cc i ppes v pp erase suspend current 1,4 0.5 1 a v pp = v pp1 erase suspend in progress 50 200 a v pp = v pp2 (12 v) erase suspend in progress i ppws v pp program suspend current 1,4 0.5 1 a v pp = v pp1 program suspend in progress 50 200 a v pp = v pp2 (12 v) program suspend in progress
28F160C18 e 28 advance information 4.4 dc characteristics, continued v cc 1.65 v C1.95 v v ccq 1.65 vC1.95 v sym parameter note min max unit test conditions v il input low voltage -0.4 0.4 v v ih input high voltage v ccq - 0.4 v v ccq + 0.3 v v v ol output low voltage 7 -0.10 0.10 v v cc = v cc min v ccq = v ccq min i ol = 100 m a v oh output high voltage 7 v ccq - 0.1 v v v cc = v cc min v ccq = v ccq min i oh = C100 m a v pplk v pp lock-out voltage 3 0.4 v complete write protection v pp1 v pp during program / erase 3 0.9 1.95 v v pp2 operations 3,6 11.4 12.6 v lko v cc prog/erase lock voltage 1.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc , t a = +25 c. 2. i cces and i ccws are specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . if the device is read while in program suspend, current draw is the sum of i ccws and i ccr . 3. erase and program are inhibited when v pp < v pplk and not guaranteed outside the valid v pp ranges of v pp1 and v pp2 . 4. sampled, not 100% tested. 5. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 6. applying v pp = 11.4 vC12.6 v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. v pp may be connected to 12 v for a total of 80 hours maximum. see section 3.5 for details. 7. the test conditions v cc max, v ccq max, v cc min, and v ccq min refer to the maximum or minimum v cc or v ccq voltage listed at the top of each column.
e 28F160C18 29 advance information input output test points v ccq 0.0 v ccq 2 v ccq 2 0645_07 figure 5. input/output reference waveform device under test out r 1 v ccq c l r 2 0645_08 figure 6. test configuration test configuration component values table test configuration c l (pf) r 1 ( w )r 2 ( w ) 1.65 v C1.95 v standard test 50 14.5k 14.5k note: c l includes jig capacitance.
28F160C18 e 30 advance information 4.5 ac characteristics read operations (1,4) extended temperature product 16 mbit access time (ns) 90 120 # symbol parameter note min max min max unit r1 t avav read cycle time 90 120 ns r2 t avqv address to output delay 90 120 ns r3 t elqv ce# to output delay 2 90 120 ns r4 t glqv oe# to output delay 2 45 45 ns r5 t phqv rst# to output delay 150 150 ns r6 t elqx ce# to output in low z 3 0 0 ns r7 t glqx oe# to output in low z 3 0 0 ns r8 t ehqz ce# to output in high z 3 25 25 ns r9 t ghqz oe# to output in high z 3 25 25 ns r10 t oh output hold from address, ce#, or oe# change, whichever occurs first 30 0 ns notes: 1. see figure 7: ac waveform: read operations . 2. oe# may be delayed up to t elqv Ct glqv after the falling edge of ce# without impact on t elqv . 3. sampled, but not 100% tested. 4. see figure 5: input/output reference waveform for timing measurements and maximum allowable input slew rate.
e 28F160C18 31 advance information address stable device and address selection ih v il v addresses (a) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) data (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 figure 7. ac waveform: read operations
28F160C18 e 32 advance information 4.6 ac characteristics write operations (1,5,6) extended temperature product 16 mbit access time (ns) 90 120 # symbol parameter note min min unit w1 t phwl / t phel rst# high recovery to we# (ce#) going low 150 150 ns w2 t elwl / t wlel ce# (we#) setup to we# (ce#) going low 0 0 ns w3 t wlwh / t eleh we# (ce#) pulse width 4 70 70 ns w4 t dvwh / t dveh data setup to we# (ce#) going high 2 70 70 ns w5 t avwh / t aveh address setup to we# (ce#) going high 2 70 70 ns w6 t wheh / t ehwh ce# (we#) hold time from we# (ce#) high 0 0 ns w7 t whdx / t ehdx data hold time from we# (ce#) high 2 0 0 ns w8 t whax / t ehax address hold time from we# (ce#) high 2 0 0 ns w9 t whwl / t ehel we# (ce#) pulse width high 4 30 30 ns w10 t vpwh / t vpeh v pp setup to we# (ce#) going high 3 200 200 ns w11 t qvvl v pp hold from valid srd 3 0 0 ns w12 t bhwh / t bheh wp# setup to we# (ce#) going high 3 0 0 ns w13 t qvbl wp# hold from valid srd 3 0 0 ns w14 t whgl write recovery before read 3,7 30 ns notes: 1. write timing characteristics during erase suspend are the same as during write-only operations. 2. refer to table 5 for valid a in or d in . 3. sampled, but not 100% tested. 4. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . similarly, write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl . 5. see figure 5: input/output reference waveform for timing measurements and maximum allowable input slew rate. 6. see figure 8: ac waveform: program and erase operations 7. delay is defined from we#(ce#) high to oe# going low.
e 28F160C18 33 advance information 4.7 erase and program timings (1) v pp 0.9 v C1.95 v 11.4 vC12.6 v symbol parameter note typ (1) max typ (1) max unit t bwpb 4-kw parameter block program time (word) 2, 3 0.1 0.3 0.03 0.1 s t bwmb 32-kw main block program time(word) 2, 3 0.8 2.4 0.24 0.80 s t whqv1 / t ehqv1 word program time 2, 3 22 200 8 185 s t whqv2 / t ehqv2 4-kw parameter block erase time (word) 2, 3 1 4 0.8 4 s t whqv3 / t ehqv3 32-kw main block erase time (word) 2, 3 1.8 5 1.1 5 s t whrh1 / t ehrh1 program suspend latency 3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 3 5 20 5 20 s notes: 1. typical values measured at t a = +25 c and nominal voltages. 2. excludes external system-level overhead. 3. sampled, but not 100% tested.
28F160C18 e 34 advance information a in a in ab c d e f w11 d in w10 valid srd d in d in w7 w3 w4 high z w2 w9 w6 w5 w8 v ih v il addresses [a] v ih v il ce# (we#) [e(w)] v ih v il oe# [g] v ih v il we# (ce) [w(e)] v ih v il data [d/q] v ih v il wp# v pph 1 v il v pp [v] v pph 2 v ih v il rp# [p] (note 1) (note 1) w13 w12 w1 v pplk notes: 1. ce# must be toggled low when reading status register data. we# must be inactive (high) when reading status register data. a. v cc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. write read array command. figure 8. ac waveform: program and erase operations
e 28F160C18 35 advance information 4.8 reset operations ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plrh t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t figure 9. ac waveform: reset operation table 11. reset specifications (1) v cc 1.65 v C1.95 v symbol parameter notes min max unit t plph rst# low to reset during read (if rst# is tied to v cc , this specification is not applicable) 2,4 100 ns t plrh1 rst# low to reset during block erase 3,4 22 s t plrh2 rst# low to reset during program 3,4 12 s notes: 1. see section 3.1.4 for a full description of these conditions. 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. if rst# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. sampled, but not 100% tested.
28F160C18 e 36 advance information 5.0 ordering information t e 2 8 f 1 6 0 c 1 t 9 0 package te = 48-lead tsop bg = 55-ball 0.5 mm bga* csp product line designator for all intel ? flash products access speed (ns) 16 mbit = 90, 120 product family c18 = 1.8 v advanced+ boot block v cc = 1.65 v - 1.95 v v pp = 0.9 v - 1.95 v or 11.4 v - 12.6 v device density 160 = x16 (16 mbit) t = top blocking b = bottom blocking 8 valid combinations (all extended temperature) 48-lead tsop 48-ball m bga* csp extended 16m te28F160C18t90 bg28F160C18t90 te28F160C18b90 bg28F160C18b90 te28F160C18t120 bg28F160C18t120 te28F160C18b120 bg28F160C18b120 notes: 1. the 48-ball bga package top side mark reads fxx0c18 where xx is the device density.
e 28F160C18 37 advance information 6.0 additional information (1,2) order number document/tool 210830 flash memory databook 292215 ap-657 designing with the advanced+ boot block flash memory architecture 292204 ap-646 common flash interface (cfi) and command sets contact your intel representative flash data integrator (fdi) software developers kit 297874 fdi interactive: play with intels flash data integrator on your pc notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com or http://intel.com/design/flash for technical documentation and tools.
28F160C18 e 38 advance information appendix a wsm current/next states command input (and next state) current state sr.7 data when read read array (ffh) program setup (10/40h) erase setup (20h) erase confirm (d0h) prog/ers suspend (b0h) prog/ers resume (d0) read status (70h) clear status (50h) read array 1 array read array program setup erase setup read array read status read array read status 1 status read array program setup erase setup read array read status read array read config. 1 config read array program setup erase setup read array read status read array read query 1 cfi read array program setup erase setup read array read status read array lock setup 1 status lock command error lock (done) lock cmd. error lock (done) lock cmd. error lock cmd. error 1 status read array program setup erase setup read array read status read array lock oper. (done) 1 status read array program setup erase setup read array read status read array prot. prog. setup 1 status protection register program prot. prog. (not done) 0 status protection register program (not done) prot. prog. (done) 1 status read array program setup erase setup read array read status read array prog. setup 1 status program program (not done) 0 status program (not done) prog. sus. status program (not done) prog. susp. status 1 status prog. sus. read array program suspend read array program (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read array 1 array prog. sus. read array program suspend read array program (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read config 1 config prog. sus. read array program suspend read array program (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array prog. susp. read query 1 cfi prog. sus. read array program suspend read array program (not done) prog. sus. rd. array program (not done) prog. sus. status prog. sus. rd. array program (done) 1 status read array program setup erase setup read array read status read array erase setup 1 status erase command error erase (not done) erase cmd. error erase (not done) erase command error erase cmd. error 1 status read array program setup erase setup read array read status read array erase (not done) 0 status erase (not done) erase sus. status erase (not done) ers. susp. status 1 status erase sus. read array program setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase susp. array 1 array erase sus. read array program setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read config 1 config erase sus. read array program setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array ers. susp. read query 1 cfi erase sus. read array program setup ers. sus. rd. array erase ers. sus. rd. array erase erase sus. status ers. sus. rd. array erase (done) 1 status read array program setup erase setup read array read status read array
e 28F160C18 39 advance information appendix a wsm current/next states (continued) command input (and next state) current state read config (90h) read query (98h) lock setup (60h) prot. prog. setup (c0h) lock confirm (01h) lock down confirm (2fh) unlock confirm (d0h) read array read config. read query lock setup prot. prog. setup read array read status read config. read query lock setup prot. prog. setup read array read config. read config. read query lock setup prot. prog. setup read array read query read config. read query lock setup prot. prog. setup read array lock setup locking command error lock operation (done) lock cmd. error read config. read query lock setup prot. prog. setup read array lock operation (done) read config. read query lock setup prot. prog. setup read array prot. prog. setup protection register program prot. prog. (not done) protection register program (not done) prot. prog. (done) read config. read query lock setup prot. prog. setup read array prog. setup program program (not done) program (not done) prog. susp. status prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read array prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read config. prog. susp. read config. prog. susp. read query program suspend read array program (not done) prog. susp. read query. prog. susp. read config. prog. susp. read query program suspend read array program (not done) program (done) read config. read query lock setup prot. prog. setup read array erase setup erase command error erase (not done) erase cmd. error read config. read query lock setup prot. prog. setup read array erase (not done) erase (not done) erase suspend status erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) erase suspend array erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read config erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) eras sus. read query erase suspend read config. erase suspend read query lock setup erase suspend read array erase (not done) ers.(done) read config. read query lock setup prot. prog. setup read array
28F160C18 e 40 advance information appendix b program/erase flowcharts start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 command program setup program comments data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error figure 10. automated word programming flowchart
e 28F160C18 41 advance information start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data=70h addr=x command program suspend read status read array program resume figure 11. program suspend/resume flowchart
28F160C18 e 42 advance information start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby command erase setup erase confirm comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted figure 12. automated block erase flowchart
e 28F160C18 43 advance information start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 read array data from block other than the one being erased. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = x bus operation write standby write read standby read command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write data=70h addr=x command erase suspend read status read array erase resume figure 13. erase suspend/resume flowchart
28F160C18 e 44 advance information start write 60h (configuration setup) read status register no comments data = 60h addr = x sr.4, sr.5, sr.7 = write 90h (read configuration) read block lock status locking change confirmed? locking change complete 80h check status register 80h = no error b0h = lock command sequence error bus operation write command b0h write 01h, d0h, or 2fh status register data addr = x write write read (optional) standby (optional) data= 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr=within block to lock command config. setup lock, unlock, or lockdown lock command sequence error data = 90h addr = x write (optional) read configuration block lock status data addr = second addr of block read (optional) block lock status confirm locking change on dq 1 , dq 0 . (see block locking state table for valid combinations.) standby (optional) figure 14. locking operations flowchart
e 28F160C18 45 advance information start write c0h (protection reg. program setup) write protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error protection register programming error attempted program to locked register - aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1, 1 0,1 1,1 command protection program setup protection program comments data = c0h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments sr.1 sr.3 sr.4 0 1 1 v pp low 0 0 1 prot. reg. prog. error 1 0 1 register locked: aborted read status register data toggle ce# or oe# to update status register data standby figure 15. protection register programming flowchart
28F160C18 e 46 advance information appendix c common flash interface query structure this appendix defines the data structure or database returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. c.1 query structure output the query database allows system software to gain critical information for controlling the flash com ponent. this section describes the devices cfi - compliant interface that allows the host system to access query data. query data are always presented on the lowest - order data outputs (dq 0-7 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, q, r, and y in ascii, appear on the low byte at word addresses 10h, 11h, and 12h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii q in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. in addition, since the upper byte of word - wide devices is always 00h, the leading 00 has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table c1. summary of query structure output as a function of device and mode device location query data (hex, ascii) 16-mbit x 16 10 51 q (word addresses) 11 52 r 12 59 y
e 28F160C18 47 advance information table c2. example of query structure output for x16 devices device address word addressing: query data a 19 Ca 0 d 15 Cd 0 000010h 000011h 000012h 000013h 000014h 000015h 000016h 000017h 000018h ... 0051h q 0052h r 0059h y p_id lo prvendor id# (lo byte) p_id hi prvendor id# (hi byte) p lo prvendor tbladdr (lo) p hi prvendor tbladdr (hi) a_id lo altvendor id# (lo) a_id hi altvendor id# (hi) ... c.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. note: detailed sections describe the query structure sub-sections in detail are tbd.
28F160C18 e 48 advance information appendix d architecture block diagram output multiplexer 4-kword parameter block 32-kword main block 32-kword main block 4-kword parameter block y-gating/sensing write state machine program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder power reduction control input buffer output buffer gnd v cc v pp ce# we# oe# rst# command user interface input buffer a 0 -a 19 dq 0 -dq 15 v ccq wp#
e 28F160C18 49 advance information appendix e word-wide memory map diagrams 16-mbit word-wide memory addressing top boot bottom boot size (kw) 16m size (kw) 16m 4 ff000-fffff 32 4 fe000-fefff 32 4 fd000-fdfff 32 4 fc000-fcfff 32 4 fb000-fbfff 32 4 fa000-fafff 32 4 f9000-f9fff 32 4 f8000-f8fff 32 32 f0000-f7fff 32 32 e8000-effff 32 32 e0000-e7fff 32 32 d8000-dffff 32 32 d0000-d7fff 32 32 c8000-cffff 32 32 c0000-c7fff 32 32 b8000-bffff 32 32 b0000-b7fff 32 32 a8000-affff 32 32 a0000-a7fff 32 32 98000-9ffff 32 32 90000-97fff 32 32 88000-8ffff 32 32 80000-87fff 32 32 78000-7ffff 32 32 70000-77fff 32 32 68000-6ffff 32 32 60000-67fff 32 32 58000-5ffff 32 32 50000-57fff 32 32 48000-4ffff 32 32 40000-47fff 32 32 38000-3ffff 32 this column continued on next page this column continued on next page
28F160C18 e 50 advance information 16-mbit word-wide memory addressing (continued) top boot bottom boot size (kw) 16m size (kw) 16m 32 30000-37fff 32 f8000-fffff 32 28000-2ffff 32 f0000-f7fff 32 20000-27fff 32 e8000-effff 32 18000-1ffff 32 e0000-e7fff 32 10000-17fff 32 d8000-dffff 32 08000-0ffff 32 d0000-d7fff 32 00000-07fff 32 c8000-cffff 32 32 c0000-c7fff 32 32 b8000-bffff 32 32 b0000-b7fff 32 32 a8000-affff 32 32 a0000-a7fff 32 32 98000-9ffff 32 32 90000-97fff 32 32 88000-8ffff 32 32 80000-87fff 32 32 78000-7ffff 32 32 70000-77fff 32 32 68000-6ffff 32 32 60000-67fff 32 32 58000-5ffff 32 32 50000-57fff 32 32 48000-4ffff 32 32 40000-47fff 32 32 38000-3ffff 32 32 30000-37fff 32 32 28000-2ffff 32 32 20000-27fff 32 32 18000-1ffff 32 32 10000-17fff 32 32 08000-0ffff 32 4 07000-07fff 32 4 06000-06fff 32 4 05000-05fff 32 4 04000-04fff 32 4 03000-03fff 32 4 02000-02fff 32 4 01000-01fff 32 4 00000-00fff
e 28F160C18 51 advance information appendix f device id table read configuration addresses and data item address data manufacturer code x16 00000 0089 device code 16-mbit x 16-t x16 00001 88c2 16-mbit x 16-b x16 00001 88c3 note: other locations within the configuration address space are reserved by intel for future use.
28F160C18 e 52 advance information appendix g protection register addressing word-wide protection register addressing word use a7 a6 a5 a4 a3 a2 a1 a0 lock both 1 0 0 0 0 0 0 0 0 factory 1 0 0 0 0 0 0 1 1 factory 1 0 0 0 0 0 1 0 2 factory 1 0 0 0 0 0 1 1 3 factory 1 0 0 0 0 1 0 0 4 user 1 0 0 0 0 1 0 1 5 user 1 0 0 0 0 1 1 0 6 user 1 0 0 0 0 1 1 1 7 user 1 0 0 0 1 0 0 0 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a 19 Ca 8 = 0.

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